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xr-t6166 ...the analog plus company tm codirectional digital data processor rev. 2.02 1990 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 (510) 668-7010 1 june 19973 features low power cmos technology all receiver and transmitter inputs and outputs are ttl compatible transmitter inhibits bipolar violation insertion for transmission of alarm conditions alarm output indicates loss of received bipolar violations tolerance of 125 m s variance of data transfer timing in both transmit and receive paths allows operation in plesiochronous networks both receiver and transmitter perform byte insertion or deletion in response to local clock slips and provide outputs indicating slip logic activity applications ccitt g.703 compliant 64kbps codirectional interface performs the digital and analog functions for a complete 64kbps data adaption unit (dau) when used with the xr-t6164 general description the xr-t6166 is a cmos device which contains the digital circuitry necessary to interface both directions of a 64kbps data stream to 2.048mbps transmit and receive pcm time-slots. the xr-t6166 and the companion xr-t6164 line interface chip together form a ccitt g.703 compliant 64kbps codirectional interface. the xr-t6166 contains separate transmit and receive sections. the transmitter transforms 8 bit serial data from a 2.048mbps time-slot into an encoded 64kbps data stream. the receiver, which performs the reverse operation, decodes the 64kbps data, extracts a clock signal, and then outputs the data to a 2.048mbps time-slot. the xr-t6166 provides features which allow the repetitions and deletions of both received and transmitted data as clock skews and transients occur. these slip occurrences are indicated by byte insertion and deletion flags. outputs are also provided for extracted receive clock and clock recovery circuit loss of lock. ordering information part no. package operating temperature range xr-t6166cp 28 lead 600 mil pdip 0 c to +70 c xr-t6166ip 28 lead 600 mil pdip 40 c to 85 c xr-t6166cd 28 lead 300 mil jedec soic 0 c to +70 c xr-t6166id 28 lead 300 mil jedec soic 40 c to 85 c
xr-t6166 2 rev. 2.02 byte deletion 19 pcmin 20 tx2mhz 10 ts1t 15 ttsel 12 ts2t time-slot mux 8 bit latch 8 load 8 8 bit output register q load clk byte insertion 11 bdt 18 bit 13 t+r violation insertion coding logic octet counter 16 alarmin control circuitry 17 tx256khz 14 t-r clk clk d d q q figure 1. xr-t6166 transmitter section block diagram 8 bit input register d clk 1 alarm violation loss alarm data decoder clk 2 s+r 3 s-r byte sync detection clk 5 rx2mhz 23 ts1r 4 bls time slot mux 8 bit reg 0 d clk q 8 bit reg 1 d clk q register select logic 28 pcmout 26 bir 25 bdr byte insertion byte deletion reg 0 sel reg 1 sel time-slot 24 ts2r 27 rtsel 6 blank 9 rxck2mhz clock recovery 128khz recovered clock 22 cs 7 rxckout figure 2. xr-t6166 receiver section block diagram time-slot mux
xr-t6166 3 rev. 2.02 pin configuration 13 16 14 15 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 11 18 12 17 pcmout rtsel bir bdr ts2r ts1r cs v ss alarm s+r s-r bls rx2mhz blank rxckout v dd tx2mhz rxck2mhz pcmin ts1t bit bdt tx256khz ts2t alarmin t+r ttsel t-r 28 lead pdip (0.600o) 28 1 15 14 2 3 4 5 6 7 17 16 8 9 19 18 10 11 23 22 21 20 27 26 25 24 12 13 pcmout rtsel bir bdr ts2r ts1r cs v ss alarm s+r s-r bls rx2mhz blank rxckout v dd tx2mhz rxck2mhz pcmin ts1t bit bdt tx256khz ts2t alarmin t+r ttsel t-r 28 lead soic (jedec, 0.300o) pin description pin # symbol type description 1 alarm o octet timing alarm . when active, indicates loss of received bipolar violations that are used for octet timing. active high. 2 s+r i positive ami data to receiver. positive data from the xr-t6164 receive-side. active low. 3 s-r i negative ami data to receiver. negative data from the xr-t6164 receive-side. active low. 4 bls i byte locking supervision. when active, causes blanking of pcmout under received alarm conditions. active low. 5 rx2mhz i receiver 2.048mhz clock . used to clock out pcm data. 6 blank i pcmout data blanking . when active, forces pcmout data to all ones (ais). active high. 7 rxckout o 128khz extracted clock. clock recovered from received data. 8 v dd +5v 10% power source. 9 rxck2mhz i 2.048mhz clock. used by receiver clock recovery circuit. 10 ts1t i transmitter time-slot 1 input . 11 bdt o transmitter byte deletion flag . active when a transmit byte is deleted. active high. 12 ts2t i transmitter time-slot 2 input. 13 t+r o transmit positive ami data output . data to xr-t6164 positive transmitter input. active low. 14 t-r o transmit negative ami data output. data to xr-t6164 negative transmitter input. active low. 15 ttsel i transmit time-slot select. when high, pin 10 is selected; when low, pin 12 is selected. 16 alarmin i alarm input. when active, inhibits insertion of violations used for octet timing in transmitter output. active high.
xr-t6166 4 rev. 2.02 pin description (cont'd) pin # symbol type description 17 tx256khz i transmitter 256khz clock . used to output 64kbps encoded data. 18 bit o transmitter byte insertion flag. active when a transmit byte is repeated. active high. 19 pcmin i transmitter pcm input. data read from the system pcm bus. 20 tx2mhz i transmitter 2.048mhz clock. clocks pcm data in pcmin. 21 v ss ground. 22 cs o clock seek. indicates that clock recovery circuit has loss of lock with received data. active high. 23 ts1r i receiver time-slot 1 input. 24 ts2r i receiver time-slot 2 input. 25 bdr o receiver byte deletion flag. active when received data byte is deleted. active high. 26 bir o receiver byte insertion flag . active when a received data byte is repeated. active high. 27 rtsel i receive time-slot select . when high, pin 23 is selected; when low, pin 24 is selected. 28 pcmout o received pcm output data . data sent to the system pcm bus.
xr-t6166 5 rev. 2.02 electrical characteristics test conditions: v dd = 5v 10%, t a = 25 c, unless otherwise specified symbol parameter min. typ. max. unit conditions dc electrical characteristics v ih logic 1 2.4 v v il logic 0 0.4 v v dd supply 4.5 5.5 v i dd supply current 500 m a dynamic supply current i il input leakage 1 m a v ol 0.4 v at 1.6ma v oh 2.4 ma at 0.4ma ac electrical characteristics general tr, tf output rise/fall time 20 ns all outputs receiver trs rx2mhz rising edge to ts rising edge set up time 0 trxl- 100 ns figure 3 trh rx2mhz rising edge to ts falling edge hold time 0 trxl- 100 ns figure 3 tdrs ts rising edge to leading edge of pcmout d0 bit delay 10 ns figure 3 tdrh ts falling edge to trailing edge of pcmout d7 bit hold time 0 10 ns figure 3 trxd rx2mhz rising egde to pcmout bits d1 through d6 rising edge delay 10 ns figure 3 tpw pcmout pulse width 488 ns figure 3 trxh rx2mhz high time 244 ns figure 3 trxl rx2mhz low time 244 ns figure 3 trxclk rx2mhz period 488 ns 100ppm transmitter tts ts rising edge to tx2mhz set up time 20 ttxl- 100 ns figure 5 tth ts falling edge to tx2mhz hold time 0 ttxl- 100 ns figure 5 tds pcmin edge to tx2mhz set up time 100 ns figure 5 tdh pcmin edge to tx2mhz hold time 100 ns figure 5 ttxh tx2mhz high time 244 ns figure 5 ttxl tx2mhz low time 244 ns figure 5 ttxclk tx2mhz period 488 ns 100ppm
xr-t6166 6 rev. 2.02 electrical characteristics (cont'd) symbol parameter min. typ. max. unit conditions ac electrical characteristics (cont'd) transmitter (cont'd) tkxh tx256khz high time 1.95 m s tkxl tx256khz low time 1.95 m s tkxclk tx256khz period 3.9063 m s tbdth bdt high time 488 ns tbith bit high time 12.5 m s talh alarmin high time 15.6 m s specifications are subject to change without notice absolute maximum ratings supply voltage 20v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature 0 c to +70 c . . . . . . . . . . . . . storage temperature -65 c to +150 c . . . . . . . . . . . . magnetic supplier information: pulse telecom product group p.o. box 12235 san diego, ca 92112 tel. (619) 674-8100 fax. (619) 674-8262 transpower technologies, inc. 24 highway 28, suite 202 crystal bay, nv 89402-0187 tel. (702) 831-0140 fax. (702) 831-3521
xr-t6166 7 rev. 2.02 trcks trckp s+r s-r rxckout trxclk trxh trh tdrs tdrh tpw d0 d1 d2 d3 d4 d5 d6 d7 rx2mhz time-slot pcmout ttxclk ttxh ttxl tts tth tds tdh d0 d1 d2 d3 d4 d5 d6 d7 tx2mhz time-slot pcmin figure 3. receive time-slot timing figure 4. extracted clock timing figure 5. transmit time-slot timing tkxclk tkxh tkxl tr tf v ih v ih v il v il 50% 50% clock 50% figure 6. clock timing trxl trs trxd
xr-t6166 8 rev. 2.02 system description transmitter figure 1 shows the xr-t6166 transmitter section block diagram. the transmitter converts eight bit bursts or octets of 2.048mbps serial data present in a pcm time-slot to a coded continuous 64kbps data stream. during operation, data input is controlled by external clock and time-slot signals, and the 64kbps data output is timed by an external 256khz clock. since the input and output rates may not be exactly equal because of slight clock rate differences, periodic slips can occur. therefore, circuitry is included to delete or repeat octets, if necessary. transmitter operation is as follows. pcm data is applied to pcmin (pin 19), a 2.048mhz local clock is applied to tx2mhz (pin 20), and a time-slot signal is applied through the time-slot multiplexer. this multiplexer allows the transmitter to be hard wired to two time-slot positions. a time-slot signal is applied to multiplexer inputs ts1t (pin 10) or ts2t (pin 12), and a time-slot select logic level is applied to ttsel (pin 15). a high level at ttsel selects ts1t while a low level enables ts2t. the time-slot is an envelope derived externally from tx2mhz that covers eight clock pulses. the rising edge of the time-slot signal should be made to coincide with the falling edge of tx2mhz. eight bits of pcm data are clocked into the transmitter input register on the rising edge of tx2mhz while the selected time-slot signal is high. the input register data is then transferred to a storage latch. transmission of 64kbps data is controlled by the 256khz local clock that is applied to tx256khz (pin 17). it is not necessary for this clock to be synchronized with any other signals that are applied to the transmitter. the output process begins by transferring data from the storage latch to the output shift register after transmission of the previous eight bits of data is complete. four periods of tx256khz are required to encode each data bit. a alogic 0o applied to pcmin is coded as 0101 while a alogic 1o is coded as 0011. this data is output on either t+r (pin 13) or t-r (pin 14) according to the ami (alternate mark inversion) coding rule. note that the t+r and t-r outputs as well as the corresponding xr-t6164 transmitter inputs (tx+i/p, tx-i/p) are all active-low. therefore, a alogic 0o is coded as a 1010 and a alogic 1o as a 1100 at the bipolar transmitter output as specified by ccitt g.703. transmission of octet timing is performed by feeding the seventh and eighth data bits in each word to the same transmitter output. this function may be inhibited by setting alarmin (pin 16) high to transmit an alarm condition. should skew occur between the tx2mhz and tx256khz clocks signals, or during an adjustment of the timing of the time-slot signal, circuitry is included to delete or repeat complete words of data. this could happen, for example, when changing from one time-slot position to another. outputs are provided to indicate when a data byte is inserted or deleted. a byte repetition or insertion occurs once if no new pcm data is received. the bit flag (pin 18) is active during the transmission of inserted data. a byte repetition just occurs once. if no new pcm data is received, the t+r and t-r outputs stay high. a byte deletion occurs when the transmitter receives a new byte of data before the previous byte is transferred from the storage latch to the output register. under this condition, the stored data is overwritten and the bdt flag (pin 11) is active. receiver figure 2 shows the block diagram of the xr-t6166 receiver section. the receiver converts coded continuous 64kbps data to eight bit bursts of 2.048mbps serial data suitable for insertion in a pcm time-slot. during operation, data input is timed by a clock that is extracted from the input signal, while output is controlled by external locally supplied clock and time-slot signals. since the data input and output rates may not be exactly equal, circuitry is included to delete or repeat eight bit data blocks, if necessary. receiver operation is as follows. a line interface chip such as the receive section of the xr-t6164 converts the encoded bipolar 64kbps signal to dual-rail active-low logic levels. these signals are applied to the xr-t6166 receiver s+r (pin 2) and s-r (pin 3) inputs. a 128khz clock, which is derived from the received signal, is used to decode this data, and then to clock it into one of two storage registers. two registers are used so that one may be receiving continuous data at 64kbps while the other is sending eight bit bursts at a 2.048mbps rate to pcmout (pin 28) while the receiver time-slot signal is high. the time-slot is an envelope derived externally from rx2mhz (pin 5) that covers eight clock pulses. the rising edge of the time-slot signal should be made to coincide with the rising edge of rx2mhz. eight bits of pcm data are clocked out of the receiver register on the rising edge of rx2mhz while the
xr-t6166 9 rev. 2.02 time-slot signal is high. a two input multiplexer at the time-slot input allows the receiver to be hard wired to two time-slot positions. time-slot signals are applied to ts1r (pin 23) and ts2r (pin 24) and the active time-slot is selected by rtsel (pin 27). a high level applied to rtsel selects ts1r and a low level selects ts2r. data appearing at pcmout is framed by the read time-slot signal and is guaranteed glitch free. recovery of the 128khz timing signal is performed by a variable length counter which is clocked by the 2.048mhz signal applied to rxck2mhz (pin 9). this clock is not required to be synchronized with any other signals that are applied to the xr-t6166. however, the rx2mhz clock may also be used for this function. positive input data transitions are used to synchronize this counter with the data. if synchronization is lost, the counter length is shortened, and the clock recovery circuit enters a seek mode until a transition is found. this mode is identified by a high level at the cs output (pin 22). the extracted 128khz signal is available at rxckout (pin 7). octet timing ensures that bit grouping is maintained when the data is converted from a 64kbps continuous stream to eight bit 2.048mbps bursts. bipolar violations are used to identify the last bit in each eight bit octet. in the absence of these violations, for example when receiving a transmitted alarm condition (transmitter alarmin is high), the circuit will continue to operate in synchronization with respect to the last received violation. during this time, the data present at pcmout is still correct as long as synchronization based on the last received violation is still valid, and the bls input (pin 4) is held high. however, if bls is low and an octet timing violation is not received, receiver output data is blanked by forcing pcmout to a high level. also, if eight successive octet timing violations are not received, the alarm output (pin 1) goes to a high level. a high level applied to the blank input (pin 6) will also force pcmout to an all-ones state. slip control logic is included in the receiver to accommodate rate differences between input and output data. the 64kbps input rate is determined by the remote transmitter, while the pcmout rate is set by rx2mhz which is a local clock. if this clock is slow, an octet will be deleted periodically, while the last octet will be repeated under fast conditions. octet timing is maintained during these operations. outputs are provided to indicate when an octet is inserted or deleted. the bir flag (pin 26) is high when pcmout data is repeated, and the bdr flag (pin 25) is high when the receiver deletes an octet. application information 64kbps codirectional interface figure 7 shows a codirectional interface circuit using the xr-t6166 with the xr-t6164 line interface. the xr-t6164 first converts the bipolar 64kbps transmit and receive signals to active-low ttl compatible data required by the xr-t6166. the xr-t6166 then performs the digital functions that are necessary to interface this 64kbps continuous data to a 2.048mbps pcm time-slot. the 64kbps signals that have been attenuated and distorted by the twisted pair cable are transformer-coupled to the line side of the xr-t6164 as shown on the left side of figure 7. a suggested transformer for both the input and output applications is the pulse type pe-65535. the right side of figure 7 shows the xr-t6164 los (loss of signal) output and the xr-t6166 digital inputs and outputs. all of these pins are ttl compatible. please refer to the pin description section of this data sheet for detailed information about each signal.
xr-t6166 10 rev. 2.02 loss of tx sync byte repeat flag byte delete flag t6164 los output recovered clk data to pcm bus clk seek flag alarm 1 pcmout 28 bir 26 bdr 25 rxckout 7 cs 22 bls 4 rx2mhz 5 ts1r 23 ts2r 24 rtsel 27 blank 6 rxck2mhz 9 bdt 11 bit 18 pcmin 19 tx2mhz 20 ts1t 10 ts2t 12 ttsel 15 tx256khz 17 alarmin 16 s+r 2 s-r 3 t-r 14 t+r 13 v ss 21 v dd 8 xr-t6166 receive side transmit side +5v 0.1 m f +5v 0.1 m f 0.1 m f 0.1 m f 1:2 480 ring 0.1 m f tip rx+i/p 16 rx-i/p 1 i/p bias 2 peak cap 14 tx+o/p 10 tx-o/p 8 g n d a 4 g n d d 7 v c c d 9 c c a 13 s+r 12 s-r 5 r x a l a r m 3 t c m c o n 15 tx-i/p 6 tx+i/p 11 xr-t6164 blank o/p for alarm time-slot 1 time-slot 2 time-slot select forces all ones 2.048mhz clock byte delete flag byte insert flag time-slot 1 time-slot 2 time-slot select data from pcm bus inhibit violations 300 300 1:2 +5v 0.1 m f tip ring 64kbps data to line figure 7. typical codirectional application circuit v 2.048mhz clock 2.048mhz clock 256khz clock pe-65535 tti-17147 pe-65535 tti-17147 64kbps data to line
xr-t6166 11 rev. 2.02 transmitter code conversion figure 8 shows the transmitter code conversion process that ccitt g.703 specifies for a 64kbps codirectional interface. step 1 - a 64kbps bit period is divided into four unit intervals. step 2 - a binary 1 is coded as a 1100. step 3 - a binary 0 is coded as a 1010. step 4 - the binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks. step 5 - the alternation in polarity of the blocks is violated every eighth block. the violation block marks the last bit in an octet. bit number 64kbps data steps 1-3 step 4 step 5 octel timing violation violation 10 0 1 0 0 1 1 1 0 1 1 1 78 2 3 4 5 6 7 8 figure 8. transmitter code conversion for a 64kbps bipolar line signal
xr-t6166 12 rev. 2.02 codirectional interface pulse masks figure 9 and figure 10 show the ccitt g.703 64kbps codirectional interface pulse masks for single and double pulses respectively of either polarity. note that this mask is for the pulse measured at the xr-t6164 transmitter output (application circuit shown in figure 5 ) when terminated with a 120 w resistor. v 1.0 0.5 0 figure 9. mask for a single pulse figure 10. mask for a double pulse 7.8 m s (3.9 + 3.9) 6.5 m s (3.9 + 2.6) 4.29 m s (3.9 + 0.39) 3.9 m s 3.51 m s (3.9 -0.39) 3.12 m s (3.9 -0.78) 11.7 m s (7.8 + 3.9) 10.4 m s (7.8 + 2.6) 8.19 m s (7.8 + 0.39) 7.8 m s 7.41 m s (7.8 - 0.39) 7.02 m s (7.8 - 0.78) 0.1 0.1 2.0 2.0 0.1 0.1 0.1 0.1 2.0 2.0 0.1 0.1 0.2 0.2 v 1.0 0.5 0
xr-t6166 13 rev. 2.02 28 lead plastic dual-in-line (600 mil pdip) rev. 1.00 symbol min max min max inches a 0.160 0.250 4.06 6.35 a 1 0.015 0.070 0.38 1.78 a 2 0.125 0.195 3.18 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 1.380 1.565 35.05 39.75 e 0.600 0.625 15.24 15.88 e 1 0.485 0.580 12.32 14.73 e 0.100 bsc 2.54 bsc e a 0.600 bsc 15.24 bsc e b 0.600 0.700 15.24 17.78 l 0.115 0.200 2.92 5.08 a 0 15 0 15 millimeters 28 1 15 14 d b 1 a 1 e 1 e a l b seating plane a e c a 2 note: the control dimension is the inch column e b e a
xr-t6166 14 rev. 2.02 symbol min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.050 bsc 1.27 bsc h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 inches millimeters 28 lead small outline (300 mil jedec soic) e d e h b a l c a 1 seating plane 28 15 14
xr-t6166 15 rev. 2.02 notes
xr-t6166 16 rev. 2.02 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contains herein are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1990 exar corporation datasheet june 1997 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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